Solar cell

ABSTRACT

Provided is a solar cell having a silicon substrate for a solar cell, the substrate being formed by allowing a high-purity polycrystalline silicon layer to grow on a surface of a base that is sliced from a polycrystalline silicon ingot which is obtained by melting metal-grade silicon and solidifying the silicon in one direction, wherein a layer having a non-doped amorphous silicon phase and a microcrystalline silicon phase mixed together is stacked on the high-purity polycrystalline silicon layer.

TECHNICAL FIELD

The present invention relates to a polycrystalline silicon solar cellthat can be produced at a low cost and that hardly suffers from a limitof a silicon resource in production thereof.

BACKGROUND ART

A solar cell has been widely employed with a growing awareness of theenvironments. In the production of a general solar cell, asingle-crystalline or polycrystalline silicon substrate has been mainlyused. The single-crystalline silicon for the solar cell is basicallyformed by pulling using the Czochralski method that is also used in theproduction of silicon for semiconductor. On the other hand, thepolycrystalline silicon substrate can be produced by melting andsolidifying silicon in a crucible with higher throughput than thesingle-crystalline silicon. However, in many cases, a silicon waferwhich has been out of the standard in the IC industry or the like or aremaining pulled silicon is recycled as a raw material forpolycrystalline silicon, as a result of which the amount of supply ofthe raw material is limited, and the cost cannot be reduced so much.

Under the above circumstances, an attempt has been made to refinepolycrystalline silicon that has been produced by using inexpensiveunrefined silicon (metal-grade silicon) which has been merely reduceddirectly from silica, not through a silicon refining process forsemiconductor such as the Siemens method. For example, K. Hanazawa, M.Abe, H. Baba, N. Nakamura, N. Yuge, Y. Sakaguchi, Y. Kato, S. Hiwasa andM. Obashi have proposed a technique in which a silicon raw material forthe solar cell is obtained by removing a large amount of P and Bcontained in the metal-grade silicon by using an EB gun or a plasmatorch (12^(th) PVSEC June 1045 2001 proceeding p265-268). However, evenin this method, because it is particularly difficult to remove B,resulting in a necessity for a two-step process, the reduction of costcannot be realized as expected.

Also, an attempt has been made to directly grow the polycrystallinesilicon on a base made of a material other than silicon. However, thegrowth has to be normally conducted at a high temperature ranging from1000 to 1500° C., and it is difficult to use metal or glass as the basefrom the viewpoints of matching of the heat resistance or thecoefficient of thermal expansion with silicon. As a result, an attempthas been made to use glassy carbon or ceramics. However, there is atendency that a polycrystalline silicon film that has grown on the baseof that type is small in crystal grains, and the flatness of the surfaceof the polycrystalline silicon film becomes deteriorated, and thereforethe base of that type has not been put to practical use. Moreover,glassy carbon or ceramics is not at all an inexpensive material to beused for the solar cell.

Under the above circumstances, there has been proposed a method in whichthe solar cell is formed by using a substrate formed by allowing asilicon layer having high purity and a given thickness to grow on thebase made from inexpensive metal-grade silicon. For example, Haruo ITO,Tadashi SAITOH, Noboru NAKAMURA, Sunao MATSUBARA, Terunori WARABISAKO,and Takashi TOKUYAMA have fabricated a solar cell by way of trial, bygrowing silicon polycrystal on the base made of metal-grade siliconthrough the CVD method by using SiH₂Cl₂ (J. Crys. Growth 45(1978)446-453). Also, NOGUCHI, SANO and IWATA have also proposed a solar celldefined in claims 1 to 3 in which polycrystalline silicon that is highin purity to the semiconductor grade is allowed to grow on a base madeof solar cell metal-grade silicon (Japanese Patent Application Laid-OpenNo. H5-36611). According to those methods, the base is made of siliconalthough it is low in purity, and there arises no problem on theunmatching of the heat resistance and the coefficient of thermalexpansion. Also, because the grown polycrystalline silicon film has thecrystallinity similar to that of the base, a higher-qualitycrystallinity can grow on the metal-grade base compared with the case ofthe base made of glassy carbon or ceramics. However, in the method ofgrowing silicon from a gas phase such as the CVD method, the number offilms throwable per one batch is limited, and there arises such aproblem that a film is peeled off from an inner wall of the deviceduring growing. In addition, in the case where polycrystalline siliconis grown on a base made of silicon having a low purity such as themetal-grade silicon, impurities such as metal, B or P contained in thebase are liable to be contained in the high-purity silicon layer againafter the impurities leave in gas phase once. In that case, even if thepurity of a silicon gas to be used as a raw material is increased, thereis a high tendency that the grown silicon layer is contaminated with themetal, or reduced in resistance to the degree that the resistance isimproper for the production of the solar cell.

T. H. Wang, T. F. Ciszek, C. R. Schwertfeger, H. M. Mountinho, R. Matsonhave proposed a method in which liquid-phase growth is utilized for thegrowth of a high-purity silicon layer on a metal-grade silicon (SolarCell Materials and Solar Cells 41/42 (1996) 19-30). Also, Nishida hasproposed that a high-purity silicon layer is allowed to grow on a basemade from metal-grade silicon by the liquid-phase method so as to beused for the solar cell (Japanese Patent Application Laid-Open No.H10-98205). In the proposal by Nishida, there are disclosed variousnovel methods of the base formation as effective means for reducing thecosts of the solar cell production.

The liquid-phase growth method enables the easy growth of a thicksilicon layer, reduces a rate of wasting a silicon raw material, andtherefore is highly suited to the production of the solar cell. Also,when the degree of supersaturation of melt is managed, an influence ofthe impurities of the base on the high-purity silicon layer becomeslower than that in the case of the growth from the gas-phase, therebymaking it possible to obtain the polycrystalline silicon layer of highgrade with relatively ease. Therefore, the liquid-phase epitaxy methodis suitable for the formation of the substrate with a base made of themetal-grade silicon.

The above-mentioned solar cell using the substrate formed by allowingthe high-purity polycrystalline silicon to grow on the metal-gradesilicon base through the liquid-phase method is promising for thefuture. However, there is still a problem for the future at the presentstage where the research and development have started, in particular, aproblem on the method of producing the high-efficiency solar cell.

In general, an emitter layer having a conductivity type opposite to thatof the polycrystalline silicon layer is formed on the substrate.However, as a result of the experiment, it is found that when ahigh-resistant silicon film containing H such as amorphous Si ormicrocrystalline Si is deposited in the thickness of 1 nm to 10 nm onthe polycrystalline silicon layer to form a buffer layer, a solar cellcharacteristic, in particular, an open circuit voltage, remarkablyincreases. This has already been disclosed in Japanese PatentApplication Laid-Open Nos. H5-36611 and H5-48128. However, in thedisclosure of those applications, a non-doped amorphous Si layer is usedas a buffer layer, and a doped amorphous Si layer is used as an emitterlayer. For that reason, the conductivity of the emitter layer is notsufficiently high, and therefore an ITO layer is formed on the emitterlayer as an electrically conductive antireflection film. Because the ITOfilm is electrically conductive, it absorbs light and a generatedcurrent is lost. In the inventors' experiment, a current loss of about5% was found when an ITO film having 100 Ω in sheet resistance was used.

In the case where the doped amorphous silicon layer is used as theemitter layer, the use of an insulating film that is high intransparency instead of an ITO film makes it impossible to sufficientlyincrease the conductivity and induces a deterioration of a fill factor(FF). Also, in order to obtain the required conductivity, the dopedamorphous silicon layer has to have a thickness in the order of mm, andwhen the doped amorphous silicon layer is made so thick, light hardlyreaches the polycrystalline silicon layer of the active layer.

For that reason, it is necessary to form a doped crystalline siliconfilm as the emitter layer, and the crystalline silicon film is requiredto be formed on a non-doped buffer layer. In general, it is difficult toallow a crystalline silicon film to grow directly on an amorphoussilicon film, and the amorphous silicon layer having a certain constantthickness exists as an incubation layer. The light absorption on theamorphous silicon layer causes a reduction of the light that reaches theactive layer, whereby the generated current reduces.

As described above, many problems still remain in the fabrication of asubstrate for a solar cell, having a base of low-purity silicon such asmetal-grade silicon, and in the fabrication of the solar cell using sucha substrate.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a highly-efficientsolar cell using a substrate for a solar cell, wherein the substrate ismainly made of low-purity silicon as a raw material and can greatlyreduce the costs as compared with a conventional polycrystalline siliconsubstrate.

The present invention has been accomplished in view of the abovecircumstance, and in a preferred example of the present invention, abuffer layer consisting of a part having a crystallinity similar to thatof a high-purity polycrystalline silicon layer underneath and the restpart being an amorphous silicon layer, is formed on a silicon substratefor a solar cell, obtained by growing a high-purity polycrystallinesilicon layer on a base formed by slicing an ingot prepared by usinglow-purity silicon represented by metal-grade silicon, a polycrystallinesilicon film is grown on the buffer layer with using the crystal portionof the buffer layer as a seed to form an emitter layer of thepolycrystalline silicon film, and an SiN film is formed on the emitterlayer as an antireflection film.

In this example, however, the antireflection film is not essential.Also, the use of the silicon substrate for a solar cell obtained bygrowing the high-purity polycrystalline silicon layer on the base formedby slicing the ingot prepared by using the low-purity siliconrepresented by metal-grade silicon is advantageous from the viewpoint ofthe costs, but the effect of the present invention is obtained by othermodes.

Consequently, the most basic mode of the present invention isrepresented by a solar cell having a crystalline silicon substrate or acrystalline silicon layer, a layer in which an amorphous silicon phaseand a microcrystalline silicon phase are mixed together, and apolycrystalline silicon layer that has grown with the microcrystallinesilicon phase as a seed, which are stacked in the mentioned order. Inthis example, crystalline silicon may be a crystalline silicon wafer ora crystalline silicon layer formed on a substrate. In the presentspecification, crystal means single crystal or polycrystal. It ispractical to use a polycrystalline silicon wafer or a polycrystallinesilicon layer formed on a substrate.

Also, it is possible to preferably use a nondoped layer as the layer inwhich the amorphous silicon phase and the microcrystalline silicon phaseare mixed together.

From the viewpoint of cost reduction, there is provided a solar cellusing a solar cell silicon substrate for a solar cell, the substratebeing formed by growing a high-purity polycrystalline silicon layer onthe surface of a base formed by slicing an polycrystalline silicon ingotobtained by melting metal-grade silicon and solidifying the metal-gradesilicon in one direction, wherein a layer in which a nondoped amorphoussilicon phase and a microcrystalline silicon phase are mixed together isstacked on the high-purity polycrystalline silicon layer.

It is needless to say that an intermediate mode between theabove-mentioned basic mode and the mode provided from the viewpoint ofthe cost reduction is provided by the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a polycrystalline silicon solarcell in accordance with the present invention;

FIG. 2 a cross-sectional view showing another polycrystalline siliconsolar cell in accordance with the present invention;

FIG. 3 is a diagram showing the structure of an apparatus for producinga polycrystalline silicon ingot in accordance with a preferredembodiment of the present invention;

FIG. 4 is a diagram showing the structure of a liquid-phase growthapparatus in accordance with the preferred embodiment of the presentinvention;

FIG. 5 is a diagram showing the structure of another liquid-phase growthapparatus in accordance with the preferred embodiment of the presentinvention; and

FIG. 6 is a diagram showing the structure of a plasma film formationapparatus in accordance with the preferred embodiment of the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a description will be given in more detail of preferredembodiments of the present invention with reference to the accompanyingdrawings.

(Silicon as a Raw Material)

A silicon raw material that is most inexpensive and abundantly suppliedis metal-grade silicon obtained by directly reducing silica. Norway,Brazil, China and so on are major producing countries. In general, thepurity is nominally 97% or more, but the kind and density of impuritiesactually contained depend on silica of the raw material. A typicalexample is shown in Table 1. TABLE 1 Impurities Density Fe 1000 ppmw Al800 ppmw Cu 15 ppmw Cr 10 ppmw B 10 ppmw P 50 ppmw

Main impurities include a heavy metal such as Fe, Cr or Cu. Becausethose impurities exhibit a deep level in silicon and becomes the centerof recombination, the solar cell characteristic is remarkablydeteriorated. Moreover, since the heavy metal is liable to diffuse,contamination is liable to be widely spread in a high-purity siliconlayer growing step and a solar cell fabricating step when the heavemetal is contained in the material of the base with a high density. Inaddition, the metal impurities cohere into micro grains, as a result ofwhich the solar cell may be shunted.

Also, impurities that become dopant such as B, Al or P are contained inthe silicon raw material with a high density. The resistivity andconductivity type of the ingot are determined in accordance with thedensity of the dopant and the relative amount of a p-type dopand and ann-type dopant. The ingot may be of the p-type or n-type.

Also, even in the semiconductor-class or solar cell class silicon rawmaterial which is low in the density of the impurities other than Al, Band P, when the resistivity becomes lower than a given limit(substantially 0.1 Ω cm or less), even if the solar cell is fabricatedas it is, the obtained solar cell is low in the efficiency and is notput into practical use. Because the raw material of this type containsthe dopant impurities such as Al, B or P to the degree higher than apractical use level, and cannot be used for manufacturing the device,the raw material can be acquired remarkably inexpensively as comparedwith the normal high-purity silicon, thereby being capable ofeffectively using such a silicon raw material as a low-purity siliconraw material of the present invention.

Even when the high-purity silicon is used, it falls within the scope ofthe present invention.

(Description of a Process for Producing a Substrate for Solar Cell)

(Formation and Slice of Ingot)

A base made of polycrystalline silicon is formed by melting andsolidifying raw material silicon filled in a crucible and then slicingthe obtained ingot of polycrystalline silicon in a given thickness bymeans of a wire saw. A preferred ingot solidifying apparatus inaccordance with an embodiment of the present invention is shown in FIG.3. It is desirable that the solidification of the raw material siliconmelted in a crucible 201 gradually advances toward the upper surface ofthe crucible from the bottom of the crucible 201 (along a direction 207)while keeping the plane of an interface between a solidified portion 205and a melted portion 206. To achieve this, the temperature of threecylindrical heaters 202 disposed at side surfaces of the crucible 201 issloped from the upper portion of the crucible 201 toward the lowerportion thereof, and a support 204 of the crucible 201 is slowly moveddownward so that cooling advances. The heaters 203 is used to form thevertical temperature gradient, and crystal grains grow while extendingfrom the bottom of the crucible 201 toward the upper surface of thecrucible. The solidifying method of this type is called “unidirectionalsolidification”, and the heavy metal impurities are extruded from thesolidified portion 205 by a segregation effect toward a melted solution206 to result in decrease of the impurity density of the solidifiedpolycrystal, and the impurities are condensed to the finally remainingmelted solution. When the unidirectional solidification is appropriatelyconducted, the density of the heavy metal impurities in polycrystal canbe reduced to 1/100 or less of the raw material silicon. Nevertheless,since the recombination of carriers generated due to an incident lightincreases to deteriorate the characteristics, the polycrystallinesilicon cannot be used for manufacturing the solar cell. Also, B and Pare extremely low in segregation effect, and the density of theimpurities cannot be lowered through the unidirectional solidification.The above-mentioned method proposed by Haruo ITO, et al., aims at theremoval of B and P which cannot be removed by the unidirectionalsolidification as easy as possible. However, two more steps must beneeded as compared with those of the unidirectional solidification, as aresult of which the costs are greatly increased.

In the present invention, the heavy metal is removed by theunidirectional solidification as much as possible, but refinement otherthan the unidirectional solidification is not conducted. Therefore, asatisfactory characteristics cannot be expected even if the formedpolycrystalline silicon is used as the solar cell as it is. Also, ingeneral, the resistivity largely fluctuates due to the density of B, Alor P, and when the polycrystalline silicon is sliced to form a base,even if a high-purity silicon layer is formed on the base, the solarcell characteristics are adversely affected. In order to form an ingotof p-type as a conductivity type and the resistivity of a given value(300 mΩ or less) by using the raw material silicon of this type, a givenamount of B or Al may be added to the raw material silicon in accordancewith the source or grade of the raw material metal-grade silicon. Theamount of B or Al to be added has an upper limit and is limited to sucha degree that the crystallinity of Si is not deteriorated, inparticular, the size of the crystal grain is not remarkably decreased.For example, the amount of B is 2×10¹⁸ to 5×10¹⁹ cm⁻³, preferably 2×10¹⁸to 4×10¹⁹ cm⁻³, and the amount of Al is 1×10¹⁹ to 1×10²¹ cm⁻³,preferably 1×10¹⁹ to 5×10²⁰ cm⁻³. The reason why the added amount of Alis larger than that of B is that Al is liable to be separated in theunidirectional solidification as compared with B. The base that is thusformed from the ingot has a junction with the polycrystalline siliconthat is allowed to grow on the base, to thereby contribute to the solarcell characteristics, in particular, an improvement in an open circuitvoltage as will be described later. Moreover, even when this method isimplemented, an increase in the production costs is small unlike to therefinement.

The formed ingot is sliced into a flat plate having a thickness of 200to 350 μm by a cutter of an inner peripheral blade type or a wire saw.The use of the wire saw that is high in the productivity is preferablefor use in the solar cell. Because the ingot formed in accordance withthe present invention is formed through the unidirectionalsolidification method, the crystal grains extend particularly in thegrowth direction. In the case where the substrate is formed from thepolycrystalline silicon ingot for the solar cell, there are many casesin which the ingot is sliced along a direction perpendicularly crossingthe growth direction 207 of the crystal. However, in the case where theingot is used as the base as in the present invention, when the ingot issliced in parallel with the growth direction 207, an area per onecrystal grain increases, and the adverse effect of the grain boundary isdecreased. As a result, excellent characteristics of the solar cell areliable to be obtained. Since the cutting mark of the wire saw remains onthe base surface which is left sliced, and stains are stuck onto thebase surface, the base surface is etched. There are many cases in whichthe surface of the substrate for a solar cell is roughed by an alkalietching solution to form a texture structure. However, in case of thebase, there is many cases in which the surface configuration of asilicon layer that grows on the substrate is different from the surfaceof the original base, and the roughing of the base surface has nosignificance and may cause abnormal growth. Rather, it is preferablethat the surface of the base is planer-etched with a mixture solutionof, for example, nitric acid: acetic acid: hydrofluoric acid=300:68:32for several minutes so as to be smoothed after a solvent has beenwashed.

(Liquid-Phase Growth)

The high-purity polycrystalline silicon layer has to be formed on thelow-purity base such as the above-mentioned metal-grade silicon. As theforming method, there are the gas-phase growth and the liquid-phasegrowth, but in the present specification, the liquid-phase growth thatis advantageous from the viewpoint of the costs will be described.

In the case where a high-purity silicon wafer is used in the presentinvention, the formation of the polycrystalline silicon layer is notessential.

In the liquid-phase growth of silicon, a metal having a low meltingpoint such as tin, indium, gallium, aluminum or copper is melted, andsilicon is melted as metal in the melted metal. In particular, indium ispreferable for the growth of silicon at a high speed because the meltingpoint is appropriately low and easy to be dealt with, and it isdifficult that indium is solid-soluble in silicon. Copper is preferablefor the growth of silicon at a high rate because the solubility ofcopper to silicon is low. FIGS. 4 and 5 are cross-sectional viewsshowing a liquid-phase apparatus preferred to an embodiment of thepresent invention. First, a crucible 301 is heated by a cylindricalheater 304 that surrounds the crucible 301 so that silicon is melted ata temperature of about 600 to 1200° C. in accordance with the kind ofmelt until silicon is saturated, to thereby form a melt 302. Metal-gradesilicon that contains a large amount of impurities is improper as asilicon raw material to be melted. However, semiconductor-class (purityof about 10N to 11N) silicon is not required but solar cell class(purity of about 6N to 7N) silicon is acceptable for the silicon rawmaterial to be melted. Then, a base 305 of polycrystalline silicon isimmersed into the melt. In FIGS. 4 and 5, there are three bases, buttens or hundreds of bases can be treated for growth in accordance withthe size of crucible 301. Before the liquid-phase growth starts, it isusual that after the temperature of the melt 302 is made higher than thesaturation temperature of silicon so as to be unsaturated once, the base305 is immersed into the melt 302, and a part of bases is melted intothe melt so that the surfaces of the bases are adjusted to the melt.However, in the case where the base of metal-grade silicon is used, thisprocess is not preferable because the impurities in the base are meltedinto the melt. When the base surface is appropriately etched, and a flowof reduction gas such as hydrogen is formed within a vessel thatcontains the bases and crucible, even if the bases are immersed into themelt after the temperature of the melt is made lower than the saturationtemperature of silicon by about several to tens of ° C., the surface ofthe bases is adjusted to the melt, and there is no fear that theimpurities are melt into the metal.

After the bases 305 have been immersed into the melt 302, the melt iscooled. When the melt has been cooled, silicon that cannot be melted anymore is precipitated on the bases 305. Since the bases are composed ofpolycrystalline silicon, the precipitated silicon layer becomespolycrystal following the bases. There are many cases in which coolingis gradually conducted at a constant speed. This method is called“gradual cooling”. In the liquid-phase method, there is also a mannerthat is called “temperature difference method” in which the solid of asolute such as silicon and the bases are immersed into the melttogether, the solute is maintained relatively at a higher temperaturewhile the bases are maintained relatively at a lower temperature, thesolute is eluted and diffused from the surface of the solute solid sothat the solute is allowed to grow on the bases. The temperaturedifference method is preferably used in the growth of compoundsemiconductor that particularly requires the uniformity of the thicknessdirection of a grown film since the temperatures at the respectiveportions can be held constant from first to last. The temperaturedifference method is also preferably applied to the growth of silicon.The conductivity type and resistivity of the polycrystalline siliconlayer are affected by the melt. Indium, gallium, aluminum or the like,per se are p-type dopant, and when the metal of this type is used forthe melt, there are many cases in which the dopant is solid-solved intothe silicon and becomes of p-type. In particular, indium is hardlysolid-solved into the silicon, and the conductivity is readilycontrollable. Although, tin is slightly solid-solved into the silicon,tin is electrically inactive because of IV-group element, and theconductivity is controllable. In the case of using those melts, dopantsuch as B, aluminum, gallium, P or antimony is melted into the melt, andthe liquid-phase growth is conducted, thereby being capable of freelycontrolling p-type or n-type.

In the case where the polycrystalline silicon layer is used as an activelayer of the solar cell, the resistivity of the polycrystalline siliconlayer is preferably about 0.1 to 10 Ωcm. If the resistivity is higherthan the above upper limit, n⁺-p junction (or p⁺-n junction) between thepolycrystalline silicon layer and the emitter layer is not sufficientlyformed, and in particular, an open circuit voltage is dropped.Conversely, if the resistivity is lower than the above lower limit, adepletion layer is not sufficiently spread, and the recombination ofcarriers is also increased, and in particular, a short-circuit currentis lowered. On the contrary, it is desirable that the base is of thesame conductivity type and lower in the resistivity. With this, a p-p⁺junction (n-n⁺ junction) is formed between the polycrystalline siliconlayer and the base, a back surface field (BSF) effect is exhibited, theabsorption of a long-wavelength light is strengthened to increase theshort-circuit current, and the open circuit voltage is also improved.There are usually many cases in which the base is used as p+ (about0.005 to 0.1 Ωcm) and the polycrystalline silicon layer is used as p(about 0.1 to 10 Ωcm), but even if the base is used as n+ (about 0.005to 0.1 Ωcm) and the polycrystalline silicon layer is used as n (about0.1 to 10 Ωcm), the same effects can be obtained.

Also, in the case where the polycrystalline silicon layer is used as theactive layer of the solar cell, since the absorption of the incidentlight increases more as the polycrystalline silicon layer is thicker, itis desirable that the thickness is about 100 μm at minimum. However, along period of time is required for the growth, and the amount of rawmaterial silicon to be used increases, resulting in an increase in thecosts. Therefore, there is proposed a method in which a texturestructure is formed on the surface of the polycrystalline silicon layerby etching with an alkali solution or the like, and an optical pathlength of the incident light is extended to strength the absorption asgenerally applied in the crystalline silicon solar cell. However, thismethod is not preferable because the polycrystalline silicon layer thathas grown after all the effort is lost.

In the case where liquid-phase growth is conducted on the base which ismade of crystalline silicon, there is a case in which a specific faceorientation, in particular, a plane (facet face) having a (111) facepreferentially appears on the surface of the polycrystalline silicon.Now, this will be described with reference to FIG. 2. Because the facetface is inclined with respect to the surface of the base 101, fineconcaves and convexes having a pitch of several to tens of μm are formedon the surface of the polycrystalline silicon layer 102. In addition, inthe polycrystalline silicon base, the orientations of the facet face areuniform within one crystal gain, but the orientations are different inthe different crystal grains, and the orientations are at random as awhole. Even in the polycrystalline silicon layer 102 that is about 20 to50 μm in the thickness, the same light absorption as that of a flatpolycrystalline silicon layer that is 100 μm in the thickness isobtained due to the action of the fine concaves and convexes formed onthe facet face. This method is advantageous from the viewpoints of thecosts since all of the grown silicon are available and the etchingprocess is not required as compared with the etching method.

In the present invention, high-density dopant elements are contained inthe base. Also, in particular, in the case where metal-grade silicon isused as a raw material, heavy-metal impurities that could not be removedare contained in the base. In the case of using the base of this type,the dopant elements or the heavy-metal impurities are diffused from thesurface of the exposed base within a treating apparatus in a solar cellmanufacturing process, which may adversely affect the characteristics ofthe completed solar cell. In particular, the adverse influence is liableto appear in a thermal diffusion step for forming the emitter layer (n⁺type layer in the case where the polycrystalline silicon layer is of thep-type) of the surface, which is executed at a high temperature.Therefore, from the viewpoint of impurity diffusion prevention, it isdesirable that the overall surface of the base is covered with ahigh-purity polycrystalline silicon layer when the liquid-phase growthis conducted. On the other hand, when the back surface of the base iscovered with a polycrystalline silicon layer that is relatively high inresistance, an electric contact of the back surface is difficult toobtain. Therefore, as shown in FIGS. 1 and 2, it is possible that theliquid-phase growth is conducted in a given region of the back surfaceof the base 101 so as to expose the base surface, whereas the frontsurface and end surface of the base are perfectly covered with thepolycrystalline silicon layer 102. In the case where the substrate thusformed passes through the solar cell manufacturing process, thediffusion of the impurities can be suppressed by a method in which acover is put to the exposed portion or two substrates are put on eachother back to back. Also, since the exposed portion is low in theresistance, the electric contact with the base can be readily taken.

The apparatus shown in FIGS. 4 and 5 are equipped with a mechanism forforming the exposed portion on only the back surface of the base inconducting the liquid-phase growth. In the apparatus shown in FIG. 4,each of the bases 305 is supported between a support plate 306 and adrop preventing claw 307. In this cross-sectional view, there are shownonly two drop preventing claws 307, however in fact, the apparatus is ofthe structure in which each of the bases 305 is stably supported by atleast three drop preventing claws. In this example, when each of thebases 305 is immersed in the melt 302, as shown in FIGS. 4 and 5, eachof the bases 305 which are lower in the relative density than the melt302 attaches to the support plate 306 due to a buoyancy, and the supportplate 306 is so formed as to be slightly larger than each of the bases305. As a result, the growth occurs on the front surface and end surfaceof the base, but the growth does not occur on the back surface of thebase at all. Also, in the apparatus shown in FIG. 5, since the supportplate 306 is so formed as to be slightly smaller than the base 305, thegrowth occurs on the periphery of the back surface of the base inaddition to the front surface and end surface of the base. However, thegrowth does not occur and the exposed portion is formed in the portionthat closely attaches to the support plate 307.

(Description of the Solar Cell Manufacturing Process)

FIG. 1 shows a cross-sectional structure of the solar cell in accordancewith the present invention.

In FIG. 1, the polycrystalline silicon layer 102 is formed on the metalsilicon base 101 through the liquid-phase method.

FIG. 2 shows a cross-sectional structure of the solar cell in accordancewith the present invention. The surface of the polycrystalline siliconlayer 102 is texture-shaped.

In general, the emitter layer 106 having the conductivity type oppositeto that of the polycrystalline silicon layer 102 is formed on thepolycrystalline silicon layer 102. However, taking the experimentalresults into consideration, a high-resistant silicon film containing Hsuch as amorphous Si or microcrystalline Si is deposited in thethickness of 1 nm to 15 nm on the polycrystalline silicon layer 102, tothereby form the buffer layer 103. As a result, it has been found thatthe solar cell characteristics, in particular, the open circuit voltageis remarkably increased. This fact has been already disclosed inJapanese Patent Laid-Open Nos. H5-36611 and H5-48128. However, in all ofthose disclosures, a nondoped amorphous Si layer is used as the bufferlayer, and a doped amorphous Si layer is used as the emitter layer 106.For that reason, because the conductivity of the emitter layer 106 isnot sufficiently high, an ITO film is formed on the emitter layer 106 asthe antireflection film having conductivity. Because the ITO film iselectrically conductive, the ITO film absorbs the light, and the loss ofthe generated current appears. In the inventors' experiments, a currentloss of about 5% appears in the ITO film that is 100 Ω in the sheetresistance. In the present invention, the structure of the buffer layer103 has been studied under the condition that a transparent insulatingfilm, in particular, an SiN film is used as the antireflection film 107,and the conductivity of the emitter layer is increased.

(Emitter Layer)

As a method of forming the emitter layer 106, there are a method offurther growing a thin silicon layer doped with a dopant having a highdensity and a conductivity type opposite to that of the polycrystallinesilicon layer on the surface of the polycrystalline silicon layer 102grown in the liquid-phase, and a method of conducting the thermaldiffusion or ion implantation of the dopant on the surface of thepolycrystalline silicon layer to change the conductivity type of theuppermost surface having a thickness of thousands A if there arises noproblem on the heat resistance of the buffer layer 103. As an n-typediffusion source, it is possible that a coating solution containing P iscoated on the polycrystalline silicon layer, or a P₂O₅ layer formed onthe surface of the polycrystalline silicon by oxidizing thepolycrystalline silicon layer while an inertia gas containing POCl₃ isallowed to flow is utilized. As the p-type diffusion source, it ispossible to utilize a B₂O₃ layer formed on the surface of thepolycrystalline silicon by oxidizing the polycrystalline silicon layerwhile an inertia gas containing BBr₃ is allowed to flow. In order toobtain the emitter layer of this type due to the thermal diffusion, atemperature treatment at about 700 to 900° C. for several to tens ofminutes is required, but it is difficult to apply this method from theviewpoint of the heat resistance of the buffer layer. Normally, the filmforming method at 500° C. or lower is selected.

The depth of the junction of the emitter layer is about 1000 to 5000 Å,and the surface sheet resistance is about 10 to 500 Ω as a reference.

The electric conductivity of the amorphous Si is 10⁻⁴ S/cm even when thedopant is introduced at 10⁴ ppm as gas volume ratio, and 10⁻² S/cm evenwhen ions of about 10²¹ cm⁻³ are implanted (Applied physical datahandbook, Applied Physical Society, issued on Sep. 30, 1994).

In order to obtain the sheet resistance of 500 Ω or less by using thedoped film of amorphous Si, the thickness of 0.2 cm is required even ifthe ion implantation is conducted, which is impractical.

A crystalline silicon film is used as the emitter layer. Theconductivity depends on the amount of doping, the characteristics of thecrystalline silicon film, in particular, grain diameter. In theexperimental results of the film formed in the film forming methoddisclosed in Japanese Patent Application Laid-Open No. H8-250433 by thepresent inventors in advance, the B doped film which is thepolycrystalline film with 200 nm in the crystal grain diameter has6.7×10⁻² Ωcm in resistivity when the amount of B doping is 4.1×10¹⁹ cm⁻³In the single-crystalline silicon, taking the fact that the resistivityis 5×10⁻³ Ωcm when the amount of B doping is 2×10¹⁹ cm⁻³ intoconsideration, it is considered that the crystal grain diameter isfurther increased, and the amount of B doping is set to 10²⁰ cm⁻³ order,to thereby obtain a desired conductivity for the thickness of about 150nm.

The P doped polycrystalline film with 200 nm in the crystal graindiameter and 8×10⁻³ Ωcm in resistivity is obtained when the amount of Pdoping is 4×10²¹ cm⁻³. Accordingly, when the film thickness is 160 nm,the sheet resistance of the emitter layer can be set to 500 Ω or less.

(Buffer Layer)

An amorphous silicon layer that is not doped is introduced between thepolycrystalline silicon layer 102 and the emitter layer 103, to therebyimprove the open circuit voltage. The thickness of the amorphous siliconlayer is made uniform, and it is necessary to sufficiently thin theamorphous silicon layer so as to prevent electric charges from beingtrapped and recombined during the process. Normally, the thickness of 1nm to 5 nm is applied.

The crystalline emitter layer is formed on the amorphous silicon layer.There arise a problem. If an underlaying layer is not a crystallinesubstrate of silicon, it is difficult to directly form a crystal filmwith a large grain diameter immediately on the underlaying layer even inany one of the gas-phase method and the liquid-phase method. When theunderlaying layer is amorphous, (1) an amorphous film is formed at theinitial stage of the film formation, and after the incubation layerhaving a certain thickness has been formed, a crystal nucleus is formedand then grows into a polycrystalline film, or (2) microcrystallinegrains formed in the gas phase is deposited on the underlaying layer. Inthe case of (1), the incubation layer is amorphous, and the thicknessthereof is about 50 to 100 nm. That portion of the incubation hardlycontributes to the conductivity of the emitter layer. On the other hand,from the viewpoints of the light absorption, the incubation layer as alight absorption layer higher than the crystalline silicon by one digitis stacked by 50 to 100 nm. A light that reaches the polycrystallinesilicon layer 102 is reduced by the thickness. In the case of (2), thecrystalline grain diameter is about 10 nm, and it is difficult toincrease the conductivity even if the amount of doping increases. Forthat reason, in order to obtain the conductivity necessary for theemitter layer, the emitter layer must be thickened. For that reason,when the thickness of the emitter layer is extremely thickened, thelight absorption by the emitter layer increases, and a light thatreaches the polycrystalline silicon layer 102 reduced.

For that reason, there is applied a layer having a portion 104 in whicha part of the buffer layer 103 becomes crystalline that reflects thecrystallinity of the underlaying layer (a layer having an amorphoussilicon phase and a microcrystalline silicon phase mixed together) asshown in FIG. 2. The rate of the crystalline portion 104 and theamorphous silicon portion 105 is determined depending on whether theemitter layer can be continuously grown on the buffer layer 103 with thecrystalline portion 104 as the seed, or not. The film is formed underthe growth condition of the emitter layer which approaches the balancecondition in which the crystal growth and the etching exist together,thereby being capable of obtaining the conditions under which no film isformed on the amorphous silicon and the crystalline film extendslaterally and becomes a continuous film. When the rate of thecrystalline portion 104 is smaller, the film is formed even under thevery severe balance conditions for a long period of time.

Accordingly, the rate of the crystalline portion and the amorphousportion is selected in a range of from 1:1 to 1:10.

There are various methods of forming a film having a crystalline portionand an amorphous portion mixed together, and a typical method isdisclosed in Japanese Patent No. 2,965,094 by the present inventors. Inthis system, when infrared rays are periodically irradiated onto thepolycrystalline silicon layer 102 so that the temperature becomesslightly higher, crystalline silicon is formed on only a portion wherethe infrared rays are irradiated and the temperature becomes higher, andamorphous silicon is formed on other portions.

(Formation of Antireflection Layer and Grid Electrode)

Since silicon has a high refractive index of about 3.4 and a highreflectivity with respect to air, it is necessary to form theappropriate antireflection layer 107 on the surface of silicon. As theantireflection layer, there is used a transparent film that is about 600to 900 Å in the thickness and made of silicon nitride, titanium oxide,zinc oxide, zinc sulfide or the like which is about 1.8 to 2.3 in therefractive index and high in transparency. As the depositing method ofthe antireflection layer 107, the sputtering method, the thermal CVDmethod, the plasma CVD method or the like is generally used. In case oftitanium oxide, a coating solution can be coated and fired to form theantireflection layer 107. There is a case in which the antireflectionfilm has a function of preventing the recombination of carriers on thesurface other than the mere optical function. From this viewpoint, thesilicon nitride (SiN) film is particularly excellent, and since thesilicon nitride is liable to obtain a large current, it is widely used.

A grid electrode 108 is formed on the surface of the emitter layer inorder to take out a light current. Since the grid electrode 108 becomesa shadow with respect to the incident light, it is desirable that thewidth is as narrow as possible and the number of grid electrodes 108 isas small as possible. On the other hand, since a current is concentratedand flows in the grid electrodes, it is preferable that the resistanceis lower. Also, it is necessary that each of the grid electrodes 108 hasan excellent electric contact with the emitter layer 106. From thisviewpoint, there are generally many cases in which a pattern of silverpaste containing glass flit is printed and fired to the grid electrode108. Since the antireflection film is generally high in the resistance,it is necessary that the grid electrode 108 comes in direct contact withthe emitter layer 106. However, when the antireflection layer is formedon the grid electrode, there is an obstacle to a solder coat 109 on eachof the grid electrodes which is printed to lower the resistance of thegrid electrode. Therefore, after a region of the formed antireflectionlayer where each of the grid electrodes is to be formed is etched inadvance to expose the emitter layer, each of the grid electrodes isformed. Alternatively, there is a method (fire through method) in whichthe pattern of the grid electrodes 108 is printed on the antireflectionlayer 107, and the antireflection layer is pierced by firing so that thegrid electrodes 108 become in contact with the emitter layer 106. Thismethod starts to be popularized since the etching of the antireflectionlayer and the positioning of the grid electrode pattern are unnecessary,and the productivity is high.

(Formation of the Back Surface Electrode and Isolation of the EmitterLayer)

In the general crystalline silicon solar cell, in order to conduct anelectric contact on the back surface, in particular, in the case wherethe polycrystalline silicon layer is of the p-type, there are many casesin which aluminum paste is printed and fired to form back surfaceelectrodes. The aluminum paste is widely applied because it isrelatively inexpensive, aluminum is diffused into the substrate to forma back surface field (BSF) layer, and the use efficiency of the carriersgenerated in the vicinity of the back surface is improved to enhance thesensitivity of an incident light of a long wavelength. There are manycases in which aluminum past is contracted and bends the substrate whenaluminum paste is fired, and particularly when the electrodes are formedon an overall back surface, the bending becomes remarkable. In thispoint, since the paste is low in the resistance in the presentinvention, it is not necessary to form the back surface electrode 110 onthe entire surface at all as shown in FIG. 1, and divided pattern isavailable, and the divided pattern is readily used since the bending issmall even if the aluminum paste is used.

As described above, the emitter layer 106 is formed on the surface ofthe polycrystalline silicon layer, and when the emitter layer comes incontact with the surface of the back surface electrode or the base, alight current is leaked and the solar cell characteristics areremarkably spoiled. In the present invention, because at least the frontsurface and the end surface 105 of the base are substantially coveredwith the polycrystalline silicon layer, there is no fear that the lightcurrent is leaked. Also, in the CVD process and the thermal diffusionprocess for formation of the emitter layer, when the back surfaces ofthe substrates are put on each other back to back and processed, it isparticularly difficult that the emitter layer goes around the backsurface, and a risk of the leakage is further low. However, in the casewhere a leakage between the emitter layer 106 and the back surfaceelectrode 110 or the base 101 has particularly to be suppressed, thediffusion source of the dopant is printed by a pattern that avoids theperipheral portion of a substrate in the formation of the emitter layer,or the emitter layer on the peripheral portion of the substrate isetched and removed, or the front surface of the peripheral portion isscribed, to thereby conduct isolation. When the emitter layer on theperipheral portion of the substrate is etched or scribed, it isdesirable to substantially remove the emitter layer in a given region.Conversely, when the removal is conducted until the surface of the baseis exposed, leakage tends to occur unintentionally. Accordingly, it isnecessary to control the depth of the layer to be removed. Also, in thecase where a substantially-insulating antireflection film such as ofsilicon nitride is used, when isolation is conducted before theantireflection film is formed, the leakage preventing effect is furtherenhanced.

EXAMPLES

Examples of the present invention will be described below.

Example 1

An ingot was prepared with a mass of chemical grade metal class siliconproduced in Brazil which is 1 to 25 mm as a raw material. After the massof 1800 g was washed with acid, the mass was inserted into the apparatusshown in FIG. 3. A crucible 201 is made of carbon, and an inner surfaceof the crucible 201 is coated with SiN as a mold lubricant. The size ofthe inner surface is 80 mm in diameter×150 mm in depth. The inside ofthe apparatus was exhausted to 10 Pa, and thereafter Ar was allowed toflow into the apparatus at 1 atm. Three-stacked cylindrical side heaters202 and the upper heater 203 were controlled, the crucible was heated to1600° C., and all silicon within the crucible was melted for 10 hoursand degassing was conducted, an output of the side heaters 202 wascontrolled to form a temperature slope of 50° C. from the upper towardthe lower. In this state, a stand 204 that holds the crucible wasextremely slowly pulled down, and silicon was solidified from the bottomsurface of the crucible 201. The solidification was completed in 10hours, the outputs of both the heaters were gradually lowered, andsilicon was cooled for 10 hours. Grain boundaries extended vertically inthe solidified ingot. Reference numeral 205 denotes solidified Siportion, and reference numeral 206 is a melted Si portion. Thetemperature was controlled so that crystal grows in a direction 207 in astate where solid-liquid interface is kept horizontally. The ingot wassliced into a wafer by a band saw, the surface of the wafer was etched,and the resistivity was measured. As a result, the resistivity of then-type was 10 Ωcm. Then, the ingot was again solidified under the sameconditions except that 900 mg of B₂O₃ was added to the metal classsilicon raw material. B₂O₃ was dissolved in water and diluted, andadjusted so that a given amount of B₂O₃ was added to the silicon rawmaterial. The conductivity type of a sample to which B₂O₃ was added wasp-type, and the resistivity was 0.015 Ω/cm.

As a result of analyzing the impurities through the ICP method, thedensity of iron and chromium was 1 ppm or lower except for a portionthat extends 2.5 cm from the surface of the ingot.

The metal-grade silicon on the wafer thus obtained was used as the baseas follows. The surface of the base was subjected to planer etching witha mixed solution of nitric acid:acetic acid:hydrofluoric acid=300:68:32for two minutes to remove the cutting mark of the wire saw which remainson the base, thus obtaining a glossy surface.

A polycrystalline silicon layer was allowed to grow by a liquid-phaseapparatus shown in FIG. 4. Indium was put into the crucible 301, heatedat 930° C. and dissolved while that temperature is held. Then, a p-typesolar cell class polycrystalline silicon plate that was 3 mm in thethickness was set instead of the base, and immersed into the dissolvedindium. Silicon was dissolved into indium and saturated, and the melt302 was adjusted. The polycrystalline silicon plate was pulled up once,and the base that had been prepared in advance was mounted instead.After the atmosphere around the crucible was replaced by hydrogen, themelt 302 was cooled by 7° C. When the temperature of the melt became923° C., the base was immersed into the melt to allow to grow for onehour while the state of 930° C. is kept, and thereafter the base waspulled up from the melt. After pulling up, since a small amount ofindium stuck onto the base was found, the overall base was immersed intohydrochloric acid for one hour to remove indium. After taking out thebase 302, the polycrystalline silicon layer 102 with a thickness ofabout 30 μm grew on the base 101. The growth surface was flat.Hereinafter, the structure of the substrate and the solar cell isdescribed with reference to FIG. 1. Also, as a result of measuring theresistivity of the polycrystalline silicon layer grown grew on then-type base through the four-probes measurement, the resistivity was 0.8to 1.2 Ωcm. In this example, the reason why the n-type base was used isthat a depletion layer is formed between the base and the p-typepolycrystalline silicon layer 102, the polycrystalline silicon layer iselectrically isolated from the base, and the resistivity is measuredwith a high precision. Also, the polycrystalline silicon layercompletely covered not only the front surface of the base but also theend surface of the base, but the growth was not found on the backsurface. Thus, the solar cell polycrystalline silicon substrate wascompleted.

Subsequently, the solar cell was fabricated by using the abovepolycrystalline silicon substrate.

The substrate was installed into a plasma CVD apparatus shown in FIG. 6,a translucent mask 402 is equipped between a substrate 403 and aninfrared lamp 401 for heating the substrate, and the temperature of thesubstrate was 300° C. but was adjusted so as to periodically provide aregion of 350° C. in the form of a lattice. The periodic interval wasset to about 5 mm. Among the cyclic intervals, about 2 mm was set as ahigh-temperature region. After the inside of a chamber 400 wassufficiently exhausted, 20 sccm of SiF₄ gas and 35 sccm of H₂ gas wereintroduced into the chamber 400. A sequence that SiF₄ gas was introducedfor 10 seconds and stopped for 30 seconds is repeated. H₂ was constantlyintroduced. After the internal pressure of the chamber was set to 13 Pa,100 W of a VHF power was applied to form a film. Those conditions areone example, and largely different depending on the configuration of thechamber. What is important is conducting deposition at differenttemperatures under the conditions an amorphous silicon film and anepitaxial layer that reflects the information of an underlayingsubstrate can be formed. In this way, a buffer layer with 10 nm inthickness was formed. In the apparatus shown in FIG. 4, referencenumeral 400 denotes a chamber, reference numeral 401 denotes an infraredlamp for heating the substrate, reference numeral 402 denotes atranslucent mask, reference numeral 403 denotes a substrate, referencenumeral 404 denotes a cathode electrode, reference numeral 405 denotes amatching box, reference numeral 406 denotes a VHF power supply,reference numeral 407 denotes a pressure sensor, reference numeral 408denotes a pressure gauge and a valve open/close control device,reference numeral 409 denotes an automatic open/close valve, referencenumeral 410 denotes a thermo couple, reference numeral 411 denotes a gasjet outlet, reference numerals 412, 413 and 414 denote gas flow ratecontrol devices, respectively, reference numerals 415 to 420 denotevalves, respectively, and reference numeral 421 denotes a substrateholder.

Then, the sample was moved to another chamber of the same configuration,and the temperature of the substrate was set to 350° C. After the insideof the chamber was sufficiently exhausted, 20 sccm of SiF₄ gas, 35 sccmof H₂ gas and 10 sccm of PH₃ (PH₃/H=1%) gas were introduced into thechamber. After the internal pressure of chamber was set to 13 Pa, 100 Wof the VHF power supply was applied to form the film. In the gasintroduction sequence, (1) SiF₄ and H₂ introduction and PH₃ stop for 10seconds, (2) PH₃ and H₂ introduction and SiF₄ stop for 10 seconds, and(3) only H₂ introduction for 40 seconds were repeated. Those conditionsare one example and largely different depending on the configuration ofthe chamber, etc. In this example, there are two important points. Thatis, (1) a flat polycrystalline film is formed on a buffer layer with acrystal phase of the buffer layer as the seeds. (2) The sheet resistanceof the polycrystalline film can be set to 500 Ω or lower with thethickness of 150 nm. Also, in order to prevent a current from beingleaked at the end surface, the peripheral portion was masked forisolation at the time of forming the film.

Then, in order to form a silicon nitride film as the antireflection film107, the substrate was put into another plasma CVD chamber. Thesubstrate was mounted on a susceptor heated at a temperature of 300° C.An RF voltage was applied to a cathode that faced the substrate whileflowing silane gas, ammonium gas and nitride gas mixed together and asilicon nitride film was deposited on the surface. The deposited siliconnitride film 107 was so deposited as to also cover the end surface 106.The reflection spectrum of the surface was measured by aspectroreflectometer with an integrating sphere, and the thickness ofthe silicon nitride film and the refractive index were adjusted so thatthe reflective index is minimum at about 620 nm, and the reflectiveindex becomes 10% or lower in a range of the wavelength 450 nm to 1000nm. The film forming conditions are not particularly limited. What isimportant is the reflection spectrum.

Then, after an aluminum paste was printed as a back surface electrode110 by using a screen printing apparatus and dried, a pattern of silverpaste was printed on the surface as the grid electrode 108 and thendried. This was put into an infrared ray belt firing furnace. A zone of450° C. and a zone of 800° C. were provided in the firing furnace, twosubstrates were arranged in each of those zones, a belt was driven at aspeed of 100 mm/minute while a large amount of air was blown, and thosesubstrates passed through the respective zones to fire the pastes.Silver grains pierced through the antireflection film 107 and reachedthe emitter layer 106 to make an excellent electric contact with theemitter layer. On the other hand, the aluminum paste made an excellentelectric contact with the back surface of the base by melting aluminum.

Finally, in order to form a solder coating layer 109, the respective twosubstrates were accommodated into cassettes. The cassettes were firstimmersed in a flax tank and dried by a hot air, and immersed in a solderflow tank for a given period of time. After that, the cassette waspulled up, and dried after washing it with a hot water. The solder wascoated on only the grid of the silver paste.

In this way, the solar cell shown in FIG. 1 was fabricated.

Example 2

The buffer layer was formed in the following manner different from thatof the buffer layer formed in Example 1.

After an amorphous silicon film was formed on a substrate, an excimerlaser was periodically irradiated onto the amorphous silicon film, andan irradiated portion was crystallized. In this example, the substrateremains cooled, for example, was put on a water-cooled holder, so that anon-irradiated portion was not crystallized.

Example 3

The buffer layer was formed in the following manner different from thatof the buffer layer formed in Example 1.

A laser power in Example 2 was intensified, the amorphous silicon of theirradiated portion was gasified, and a hole from which polycrystallinesilicon formed through liquid phase on the substrate was exposed wasformed in the amorphous silicon.

Example 4

The growth conditions of polycrystalline silicon in the liquid phaseapparatus in Example 1 were set as follows. That is, indium was put intoa crucible 301, heated at 950° C. and melted while this temperature wasmaintained. Then, a p-type solar cell class polycrystalline siliconplate with 3 mm in thickness was set instead of the base and immersed inthe melted indium, and silicon was dissolved in indium, and saturated toadjust the melt 302. The polycrystalline silicon plate was pulled uponce, and a base prepared in advance was mounted instead. After theatmosphere around the crucible was replaced by hydrogen, the melt 302was cooled at a rate of 1° C. per minute. When the temperature of themelt became 945° C., the base was immersed into the melt and then pulledup after growth continued for one hour. After pulling up, since a smallamount of indium stuck onto the base was found, the overall base wasimmersed into hydrochloric acid for one hour to remove indium. Aftertaking out the base 302, the polycrystalline silicon layer 102 withabout 30 μm in thickness grew on the base 101. Hereinafter, thestructure of the substrate and the solar cell is described withreference to FIG. 2. Also, as a result of observing the surface of thesubstrate by a metallurgical microscope, fine concaves and convexeshaving a pitch of 5 to 10 μm were observed. In addition, as a resultthat the cross section of the polycrystalline silicon layer wasobserved, the concaves/convexes were structured by terraces that aredirected toward a given direction in each of the crystal grains. Theterraces were judged to be facet faces 103 that accompany the crystalgrowth. Thereafter, the same procedures as those in Example 1 wasproceeded to fabricate the solar cell with the structure shown in FIG.2.

According to the present invention, in the silicon substrate for a solarcell, formed by allowing a high-purity polycrystalline silicon layer togrow on a surface of a base sliced from a polycrystalline silicon ingotwhich is obtained by melting metal-grade silicon and solidifying thesilicon in one direction, 2×10¹⁸ cm³ to 5×10¹⁹ cm⁻³ of B or 1×10¹⁹ cm⁻³to 1×10²¹ cm⁻³ of Al is added to the metal class silicon, and thenmelted and solidified in one direction to form a polycrystalline siliconingot. With the use of this polycrystalline silicon substrate for asolar cell, a polycrystalline silicon substrate for a solar cell whichis equivalent to the conventional substrate is obtained with 1/10 of theused amount of the conventional high-purity silicon raw material. Forthat reason, the costs of the solar cell are reduced as compared withthe conventional polycrystalline silicon substrate, and productionrestrictions are small. Moreover, the substrate according to the presentinvention is equivalent in the configuration to the conventionalpolycrystalline silicon substrate, and is allowed to flow in aproduction line of the conventional solar cell with a slightmodification that does not influence the costs. Therefore, additionalinvestments in the production line of the solar cell are not required.

1. A solar cell comprising a silicon substrate for a solar cell, formedby allowing a high-purity polycrystalline silicon layer to grow on asurface of a base sliced from a polycrystalline silicon ingot which isobtained by melting metal-grade silicon and solidifying the silicon inone direction, wherein a layer having a non-doped amorphous siliconphase and a microcrystalline silicon phase mixed together is stacked onthe high-purity polycrystalline silicon layer.
 2. A solar cell accordingto claim 1, wherein a thickness of the layer having the non-dopedamorphous silicon phase and the microcrystalline silicon phase mixedtogether ranges from 1 nm to 15 nm.
 3. A solar cell according to claim 1or 2, wherein a ratio of the amorphous silicon phase and themicrocrystalline silicon phase in the layer having the non-dopedamorphous silicon phase and the microcrystalline silicon phase mixedtogether ranges from 1:1 to 10:1.
 4. A solar cell comprising acrystalline silicon substrate or a crystalline silicon layer, a layerhaving an amorphous silicon phase and a microcrystalline silicon phasemixed together, and a polycrystalline silicon layer grown with themicrocrystalline silicon phase as a seed, which are stacked in mentionedorder.